The present invention relates to telecommunications in general, and, more particularly, to an apparatus for converting one or more parallel words into one or more serialized streams of bits.
There are situations where parallel words of bits need to be transmitted via a serial communications channel. In these situations, a first apparatus converts the words into a serialized stream of bits for transmission on the serial communications channel. Typically the first apparatus is known as a serializer.
At the receiving end of the serial communications channel, a second apparatus captures the serialized stream of bits and restores it back into parallel words. Typically, the second apparatus is known as a deseriaiizer. Regardless of what the first apparatus and the second apparatus are called, the second apparatus performs the inverse operation of the first apparatus.
FIG. 1 depicts a block diagram of serial communications system 100 in the prior art, which comprises: serializer 101, deserializer 102, timing source 103, timing source 104, and serial communications channel 111, interconnected as shown.
Serializer 101 receives a parallel word of bits and a clock signal (e.g., a clock signal, etc.) from timing source 103 and converts the parallel word into a serialized stream of bits for transmission via serial communications channel 111. For example, serializer 101 can comprise a parallel-load-in/serial-shift-out register that loads words in at a slower rate than it shifts bits out.
Serial communications channel 111 is a logical data structure that can be carried alone or can be multiplexed with other serial communications channels, via a metal wireline, an optical fiber, or a wireless channel (e.g., radio, infrared, etc.).
Deserializer 102 receives the serialized stream of bits from serial communications channel 111 and a clock signal from timing source 104, captures the serialized stream of bits, and converts it back into a parallel word. For example, deserializer 102 can comprise a serial-shift-in/parallel-unload-out shift register.
The design and operation of serializer 101 can be problematic. For example, if two or more of the inputs, including the timing signal, are designed to change synchronously and yet do not, glitches (i.e., spurious signals) can appear at the output of the serializer, which compromises the integrity of the serializer.
Therefore, the need exists for a serializer whose output is free from glitches caused by the synchronous changing of its input signals.
Some embodiments of the present invention enable the serialization of bits without some of the costs and disadvantages for doing so in the prior art. For example, the illustrative embodiments of the present invention are designed so that only one input to their terminal stage can change at a time, which prevents the introduction of glitches into the serialized data stream.
Furthermore, the illustrative embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, some of the illustrative embodiments only require a tiring signal with a frequency equal to the rate at which words are loaded into them. And still furthermore, embodiments of the present invention are ideally suited for implementation in integrated circuits because they can run at a rate that is at or near the limits of the technology with which they are fabricated.
The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second unanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.